1. Technical Field
The invention relates generally to charge pump systems, and more particularly, to a charge pump system with reduced switching noise and/or low power requirements.
2. Related Art
Phase locked loop (PLL) circuits are widely used in many different applications. Three applications of PLL circuits are (1) to lock or align the output clock of a circuit with the clock input; (2) to multiply (i.e., increase) or divide (i.e., decrease) the output frequency of a circuit with respect to the input frequency; and (3) to provide clock recovery from signal noise. A phase-locked loop (PLL) circuit provides an output frequency that is adjusted to stay in sync with a reference signal.
A PLL commonly includes a charge pump and a loop filter. The charge pump controls the input voltage to a voltage controlled oscillator (VCO). The input voltage is based on inputs signals. For example, a charge pump may compare two input signals from a phase detector and vary the output voltage when the signals are out of phase. A differential charge pump may have four inputs from the phase detector and two outputs connected with a loop filter. A charge pump with a relatively high operating voltage requires a significant amount of semiconductor die space and consumes more power than a low voltage charge pump.
When a conventional PLL with a differential charge pump is locked, any mismatch in the current sources results in a leakage into the loop filter, generating sideband noise in the output signal. When the conventional charge pump's control signals are switched off, charge injection and clock feed-through results in undesirable fluctuations in the voltage from the loop filter to the VCO. The fluctuations cause the output frequency from the VCO to undesirably fluctuate.
The VCO output frequency varies based on an input voltage. A VCO typically outputs a sine wave. As the input voltage to the VCO increases, the output frequency from the VCO also increases. The dynamic range of the output voltage of a charge pump is an important factor in determining the maximum range and accuracy of the lock frequencies of the PLL.
Conventional PLLs generate noise, such as spurious sideband tones, phase noise and switching noise. In a PLL, the noise may be created by a clock source feed through, charge injection at a P-type MOSFET (PMOS) or N-type MOSFET (NMOS) switching transistor, or another source. Also, the switching nodes of conventional charge pumps often have charge sharing resulting from parasitic capacitance.
For example, the differential charge pump described in Novof et al., Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and +/−50 ps Jitter, IEEE International Solid-State Circuits Conference, 1995, pp. 112-113 exhibits charge sharing and clock feed-through.
A charge pump charges and discharges a loop filter based on the phase difference between the inputs to the charge pump. A conventional charge pump provides an output current that is the difference between an up-current from a current source connected with a supply voltage and a down-current from a current source (current sink) connected with ground. A transistor is used to turn-on or off the current source and charges the output node (i.e., increases the output voltage). Another transistor turns-on or off the current sink and discharges the output node (i.e., decreases the output voltage). A loop filter is used to reduce the output voltage fluctuations caused by switching off the up and down currents. The up and down currents should be equal to maintain a constant output voltage.
Traditionally, in a CMOS charge pump, the current source and its transistor are P-channel devices. P-channel transistors handle the supply voltage better than N-channel devices. The current sink and its transistor are N-channel devices because N-channel devices handle the reference voltage better. It is therefore desirable to have a charge pump that operates at lower power level. Further, it is desirable to eliminate noise generated by the charge pump.